Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes a semiconductor chip, a bump contact, and encapsulating layer, an insulating layer and a connection terminal.

RELATED APPLICATION

This Application is a continuation of U.S. application Ser. No. 12/039,511, filed on Feb. 28, 2008, which claims priority to Japanese Patent Application 2007-048693 filed Feb. 28,2007, both of which are incorporated by reference herein in their entirety.

TECHNICAL FIELD

This invention generally relates to a semiconductor device d a method of manufacturing the semiconductor device, and in particular, relates to a small scale semiconductor device and method of manufacturing the semiconductor device.

BACKGROUND OF THE INVENTION

Recently, there is a demand for downsizing a semiconductor device that is used for a portable electronic device such as a mobile phone or a nonvolatile record media of an IC memory card. A wafer level package (CSP) is being developed in an art where a semiconductor device is downsized.

A flip chip ball grid array (FC-BGA) is used in a conventional art of the wafer level package. A plurality of semiconductor chips are flip-chip mounted on a glass epoxy substrate and the semiconductor chips are resin-sealed with molding using an epoxy resin in order to manufacture semiconductor devices of the wafer level package. After that, an outer connection electrode such as a solder ball is connected to the glass epoxy substrate. And each of the semiconductor chips is out off with dicing. With the manufacturing hod, the wafer level package is manufactured. In accordance with the manufacturing method, a quantity of the semiconductor chips to be mounted gets larger as an area of the glass epoxy substrate gets larger. A manufacturing cost of the semiconductor device may be therefore reduced because the quantity of the semiconductor chips that are cut off with one dicing gets larger.

Japanese Patent Application Publication No. 2001-250902 (hereinafter referred to as Document 1) discloses a wafer level package in which a semiconductor chip is implanted in a ceramics substrate having a recess and a redistribution layer (RDL) is formed on the semiconductor chip. The invention disclosed in Document 1 is characterized in that the ceramics substrate having the recess is used instead of the glass epoxy substrate.

Japanese Patent Application Publication No. 2004-221417 (hereinafter referred to as Document 2) discloses a wafer level package in which a sheet-shaped insulating film having an opening according to the size of the semiconductor chip is used, the semiconductor chip is implanted in the opening, and a redistribution layer is formed on the semiconductor chip. The invention disclosed in Document 2 is characterized in that the sheet-shaped insulating film having the opening is used instead of the glass epoxy substrate and the outer connection electrode is connected to the semiconductor chip through two redistribution layers.

In accordance with the manufacturing method of the conventional art, the glass epoxy substrate may be warped because of heat generated during molding, if a large area glass epoxy substrate is used. A yield ratio of the semiconductor device may be reduced, because a problem is made in reliability of the semiconductor device when the glass epoxy substrate is warped. It is therefore difficult to use the large area glass epoxy substrate. Reduction of the manufacturing cost is limited. The glass epoxy substrate needs a certain thickness. The semiconductor chip is not able to be flip-chip mounted if the semiconductor chip does not have a certain thickness. A reduction of the height of the semiconductor device may be limited approximately 1 mm.

In accordance with the invention disclosed in Document 1, the manufacturing cost gets higher because it is necessary to form a recess on the ceramics substrate. And in accordance with the invention disclosed in Document 2, it is necessary that an insulating film should be provided according to the size of is the built-in semiconductor chip. Therefore, the manufacturing cost gets higher when various kinds of the wafer level packages are manufactured. The height of the semiconductor device gets higher, because two redistribution layers are necessary and the quantity of components is large.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device having a low height and a manufacturing cost and provides a method of manufacturing the semiconductor device.

According to an aspect of the present invention, preferably, there is provided a semiconductor device including a semiconductor chip, a bump electrode, a molding portion, a redistribution layer, and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that apart of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer. With the structure, the semiconductor device may be electrically coupled to outside with one redistribution layer. Therefore, the semiconductor device needs fewer components, compared to a semiconductor device that needs two redistribution layers in accordance with Document 2. It is therefore possible to reduce a manufacturing cost of the semiconductor device. Further, it is possible to reduce a height of the semiconductor device compared to a semiconductor device having two redistribution layers, because the semiconductor device needs only one redistribution layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross sectional view of a semiconductor device in accordance with a first embodiment;

FIG. 2A and FIG. 2B illustrate a schematic diagram accounting for an interval between each outer connection terminal and an interval between each bump electrode of the semiconductor device in accordance with the first embodiment;

FIG. 3 illustrates a schematic cross sectional view of a semiconductor device in accordance with a second embodiment;

FIG. 4 illustrates a schematic cross sectional view of a semiconductor device in accordance with a third embodiment;

FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D, and FIG. 5E illustrate a schematic cross sectional view accounting for a method of manufacturing a semiconductor device in accordance with a fourth embodiment.

FIG. 6A, 6B and FIG. 6C illustrate a schematic cross sectional view accounting for the method of manufacturing the semiconductor device in accordance with the fourth embodiment;

FIG. 7A and FIG. 7B illustrate a schematic cross sectional view accounting for the method of manufacturing the semiconductor device in accordance with the fourth embodiment; and

FIG. 8 illustrates a schematic cross sectional view accounting for the method of manufacturing the semiconductor device in accordance with the fourth embodiment.

DETAILED DESCRIPTION

A description will now be given of best modes for carrying out the present invention.

First Embodiment

FIG. 1 illustrates a schematic cross sectional view of a semiconductor device 100 in accordance with a first embodiment. As shown in FIG. 1, the semiconductor device 100 has a semiconductor chip 10, a bump electrode 12, a molding portion 14, a redistribution layer 16 and an outer connection electrode 18.

The semiconductor chip 10 is made of silicon or the like. There is provided the bump electrode 12 on an upper face of the semiconductor chip 10. The bump electrode 12 is made of Au (gold), a solder or the like, and has a height of approximately 300 μm. The molding portion 14 seals an entire side face of the semiconductor chip 10 and seals the bump electrode 12 so that a part of the bump electrode 12 is exposed. The molding portion 14 is made of an epoxy resin or the like. The molding portion 14 restrains a breaking of the semiconductor chip 10 caused by an impact from outside. There is provided the redistribution layer 16 on an upper face of the molding portion 14. The redistribution layer 16 is made of copper or the like. The redistribution layer 16 is formed with a plating method, a sputtering method or the like. The redistribution layer 16 is electrically coupled to the semiconductor chip 10 via the bump electrode 12. There is provided the outer connection electrode 18 on an upper face of the redistribution layer 16 so as to be electrically coupled to the bump electrode 12 via the redistribution layer 16. The outer connection electrode 18 is made of Au, a solder or the like, and has a height of approximately 300 μm. The outer connection electrode 18 acts as a connection terminal when the semiconductor device 100 is connected to an external circuit substrate or the like.

The semiconductor device 100 may be electrically coupled to outside with one redistribution layer. The semiconductor device 100 needs fewer components, compared to a semiconductor device that needs two redistribution layers in accordance with Document 2. It is therefore possible to reduce a manufacturing cost of the semiconductor device 100. Further, it is possible to reduce a height of the semiconductor device 100 compared to a semiconductor device having two redistribution layers, because the semiconductor device 100 needs only one redistribution layer.

It is preferable that the upper face of the bump electrode 12 and the upper face of the molding portion 14 (a face where the redistribution layer 16 is to be provided) are flat. It is possible to form the redistribution layer accurately on the upper face of the molding portion 14 with the sputtering method, the plating method or the like, when the upper face of the bump electrode 12 and the molding portion 14 is flat. It is therefore possible to improve a yield ratio of the semiconductor device 100. And it is possible to reduce the manufacturing cost of the semiconductor device 100.

It is preferable that an interval between each of the outer connection electrodes 18 is larger than that between each of the bump electrodes 12. FIG. 2A illustrates a top view of the semiconductor device 100 shown in FIG. 1. FIG. 2B illustrates a schematic view of the semiconductor device 100 shown in FIG. 2A in a case where the redistribution layer 16 and the outer connection electrode 18 are not provided. In FIG. 2B, the bump electrode 12 acts as an outer connection electrode. In FIG. 2A and FIG. 2B, intervals between each of the outer connection electrodes are referred to as “L1” and “L2” respectively.

As shown in FIG. 2A and FIG. 2B, the L1 shown in FIG. 2A is longer than the L2 shown in FIG. 2B. Generally, the L2 is reduced, when the semiconductor chip 10 is miniaturized as the semiconductor device is downsized. However, it is not easy to reduce an interval between connection terminals of the circuit substrate on the side of the semiconductor device according to the L2, even if the L2 is reduced. On the other hand, as shown in FIG. 2A and FIG. 2B, it is easy to determine a position of the semiconductor device 100 at an external circuit substrate when the semiconductor device 100 is mounted on the circuit substrate even if the semiconductor chip 10 is miniaturized, if the L1 is longer than the L2. And it is possible to restrain an electrical short between each of the outer connection electrodes 18 because the L1 is long. It is therefore possible to use the outer connection electrode 18 having a larger size. It is therefore possible to improve connection strength in a case where the semiconductor device 100 is mounted on an external circuit substrate.

Second Embodiment

A description will be given of a semiconductor device 100 a in accordance with a second embodiment. FIG. 3 illustrates a schematic cross sectional view of the semiconductor device 100 a in accordance with the second embodiment. The semiconductor device 100 a is different from the semiconductor device 100 shown in FIG. 1 in a point that a substrate 20 is further provided on a lower face of the semiconductor chip 10. The other structure is the same as that shown in FIG. 1. And an explanation of the structure is omitted.

As shown in FIG. 3, the substrate 20 is fixed to the lower face of the semiconductor chip 10 with a fixing portion 22. The fixing portion 22 is made of an adhesive resin such as an epoxy resin or the like.

The semiconductor device 100 a may be electrically connected to outside with one redistribution layer 16. Therefore, the semiconductor device 100 a needs fewer components, compared to a semiconductor device in accordance with Document 2. It is therefore possible to reduce a manufacturing cost of the semiconductor device 100 a. Further, it is possible to reduce a height of the semiconductor device 100 a compared to the semiconductor device in accordance with Document 2, because the semiconductor device 100 a has one redistribution layer 16.

It is preferable that the substrate 20 is a silicon substrate. A warpage amount of a silicon substrate caused by heat is less than that of a glass epoxy substrate. It is therefore possible to manufacture a plenty of the semiconductor devices 100 a all together if the silicon substrate is used. It is therefore possible to reduce the manufacturing cost of the semiconductor device 100 a.

Third Embodiment

A description will be given of a semiconductor device 100 b in accordance with a third embodiment. FIG. 4 illustrates a schematic cross sectional view of the semiconductor device 100 b in accordance with the third embodiment. The semiconductor device 100 b is different from the semiconductor device 100 shown in FIG. 1 in a point that an insulating portion 24 is further provided. The other structure is the same as that shown in FIG. 1. And an explanation of the structure is omitted.

As shown in FIG. 4, the insulating portion 24 is formed so that the insulating portion 24 covers the entire side face and the entire upper face of the redistribution layer 16 and a part of the outer connection electrode 18 is exposed. The insulating portion 24 is made of a resin or he like such as polyimide or the like.

In accordance with the semiconductor device 100 b, it is possible to restrain an electrical short between each of the outer connection electrodes 18, because the insulating portion 24 is provided. The yield ratio of the semiconductor device 100 b may be therefore improved and the manufacturing cost may be reduced.

The insulating portion 24 may be formed so that the insulating portion 24 covers the entire side face and the entire upper face of the redistribution layer 16 and a part of the outer connection electrode 18 is exposed in the semiconductor device 100 a in accordance with the second embodiment shown in FIG. 3. In this case, it is possible to restrain the electrical short between each of the outer connection electrodes 18 with the insulating portion 24.

Fourth Embodiment

In a fourth embodiment, a description will be given of a method of manufacturing the semiconductor device in accordance with the above-mentioned embodiment. The manufacturing method in accordance with the fourth embodiment includes a step of forming a bump electrode on a semiconductor chip, a step of fixing the semiconductor chip on a substrate, a step of forming a molding portion, a step of forming a redistribution layer and a step of forming an outer connection electrode. FIG. 5A through FIG. 5E, FIG. 6A through FIG. 6C, FIG. 7A, FIG. 7B and FIG. 8 illustrate a schematic cross sectional view accounting for the manufacturing method of the semiconductor device in accordance with the fourth embodiment.

As shown in FIG. 5A, the bump electrode 12 mad of Au, a solder or the like is formed on the upper face of the semiconductor chip 10 made of silicon or the like.

Next, as shown in FIG. 5B, the substrate 20 having a wafer shape is arranged in a mold 26 having a recess 28. The mold 26 is not limited in particular. The mold 26 may be a metallic mold. It is preferable that the substrate 20 is a silicon substrate. A warpage amount of a silicon substrate caused by heat is less than that of a glass epoxy substrate. It is therefore possible to use a silicon substrate that is a large area wafer. It is therefore possible to manufacture a plenty of the semiconductor devices all together if the silicon substrate is used. And it is possible to reduce the manufacturing cost of the semiconductor device.

Next, as shown in FIG. 5C, the semiconductor chip 10 is fixed to the upper face of the substrate 20 with the fixing portion 22. The fixing portion 22 may be made of an adhesive resin or the like such as an epoxy resin.

Next, as shown in FIG. 5D, the entire of the semiconductor chip 10 and the entire of the bump electrode 12 are sealed with an epoxy resin or the like, and are molded. Thus the molding portion 14 is formed.

In accordance with the manufacturing method, the substrate 20 having the wafer shape is arranged in the metallic mold 26 having the recess 28, and is sealed. It is therefore not necessary to provide the metallic mold 26 according to the size of each semiconductor device having different size from each other, when a various kinds of the semiconductor devices are manufactured. It is further possible to manufacture a plenty of the semiconductor devices, compared to a case where each semiconductor chip is arranged in each recess of a wafer as is the case of the manufacturing method disclosed in Document 1. It is therefore possible to reduce the manufacturing cost of the semiconductor device. In the manufacturing method disclosed in Document 1, a metallic mold having a recess is not used, but a ceramics substrate having a recess is used in a sealing step. Here, manufacturing the metallic mold 26 having the recess 28 is less expensive than manufacturing the ceramics substrate having the recess. With the method in accordance with the embodiment, it is therefore possible to reduce the manufacturing cost of the semiconductor device, compared to the manufacturing method disclosed in Document 1.

Next, as shown in FIG. 5E, the sealed semiconductor chip 10 and so on is extracted from the metallic mold 26. And the molding portion 14 is fabricated so that a part of the upper face of the bump electrode 12 is exposed. A machining process such as grinding process may be used during the fabrication of the molding portion 14. It is therefore possible to form the molding portion 14 so that the molding portion 14 seals the entire of the semiconductor chip 10 and a part of the bump electrode 12 is exposed, by fabricating the molding portion 14 so that a part of the upper face of the bump electrode 12 is exposed.

It is preferable that the molding portion 14 is fabricated so that the upper face of the molding portion 14 and the upper face of the bump electrode 12 get flat. It is possible to form the redistribution layer accurately on the upper face of the molding portion 14 with the sputtering method, the plating method or the like as described later, if the upper face of the molding portion 14 and the upper face of the bump electrode 12 are fabricated to be flat. It is therefore possible to improve the yield ratio of the semiconductor device and to reduce the manufacturing cost of the semiconductor device.

In the fourth embodiment, as shown in FIG. 5E, a description is given of a method of fabricating the molding portion 14 so that a part of the upper face of the bump electrode 12 is exposed, as a method of forming the molding portion 14 so that the molding portion 14 covers the entire of the semiconductor chip 10 and a part of the bump electrode 12 is exposed. However, the fabrication of the molding portion 14 is not always necessary if the molding portion 14 having the same structure can be formed. However, it is possible to fabricate the molding portion 14 so that the upper face of the molding portion 14 and the upper face of the bump electrode 12 get flat in the step of fabricating the molding portion 14 and to form the redistribution layer accurately, if the method includes the step of fabricating the molding portion 14. It is possible to reduce the manufacturing cost, because the yield ratio is improved if the method includes the step of fabricating the molding portion 14.

Next, as shown in FIG. 6A, there is formed the redistribution layer 16 on the upper face of the molding portion 14 so as to be electrically coupled to the bump electrode 12. The redistribution layer 16 is made of copper or the like, and is formed with the sputtering method, the plating method or the like.

Next, as shown in FIG. 6B, the insulating portion 24 is formed so that the insulating portion 24 covers the entire side face and the entire upper face of the redistribution layer 16 and a region of the redistribution layer 16 where the outer connection electrode 18 is to be connected is exposed. An insulating sheet such as polyimide may be used as the insulating portion 24. It is possible to form the insulating portion 24 so that the region of the redistribution layer 16 where the outer connection electrode 18 is to be connected is exposed, by making a hole in advance at a region of the insulating sheet where the outer connection electrode 18 is to be formed. It is not always necessary that the insulating portion 24 is formed shown in FIG. 6B. However, it is possible to restrain the electrical short between each of the outer connection electrodes 18 if the insulating portion 24 is formed. And it is possible to improve the yield ratio and to reduce the manufacturing cost.

Next, as shown in FIG. 6C, the outer connection electrode 18 made of Au or a solder is formed on the upper face of the redistribution layer 16 an that the outer connection electrode 18 is electrically coupled to the bump electrode 12 via the redistribution layer 16. With the manufacturing method in accordance with the embodiment, it is possible to manufacture the semiconductor device that is to be electrically coupled to outside with one redistribution layer. It is therefore possible to reduce the quantity of components, compared to a semiconductor device that needs two redistribution layers in accordance with Document 2. It is therefore possible to reduce the manufacturing cost of the semiconductor device. Further, it is possible to reduce the height of the semiconductor device, because the semiconductor device needs only one redistribution layer.

The substrate 20 may be removed after the formation of the outer connection electrode 18 shown in FIG. 6C. FIG. 7A illustrates a schematic cross sectional view accounting for the step of removing the substrate 20. The substrate 20 may be removed with a machining process such as a grinding process. With the method, it is possible to further reduce the height of the semiconductor device, compared to the case where the substrate 20 is provided.

And the thickness of the semiconductor chip 10 and the molding portion 14 may be reduced in the step of removing the substrate 20 shown in FIG. 7A. That is, the thickness of the semiconductor chip 10 and the molding portion 14 may be controlled to be a desirable one in the step of removing the substrate 20 with the machining process or the like. With the method, it is possible to manufacture the semiconductor device having the thickness of approximately 0.5 mm, although the thickness of the conventional semiconductor device is limited to approximately 1 mm.

And the semiconductor device may be individuated as shown in FIG. 7B after removing the substrate 20 shown in FIG. 7A. And the semiconductor device may be individuated as shown in FIG. 8 after forming the outer connection electrode 18 shown in FIG. 6C. With the methods, it is possible to manufacture the semiconductor device having one semiconductor chip 10. The substrate 20, the molding portion 14 and the insulating portion 24 may be cut off with dicing so that one semiconductor chip 10 is included in the semiconductor device, as a method of individuating the semiconductor device. In FIG. 7B and FIG. 8, the semiconductor device is individuated so that one semiconductor chip 10 is included in the semiconductor device. However, the semiconductor device may be individuated so that two semiconductor chips 10 are included in the semiconductor device.

The various aspects of the present invention are summarized below.

According to an aspect of the present invention, preferably, there is provided a semiconductor device including a semiconductor chip, a bump electrode, a molding portion, a redistribution layer, and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer. With the structure, the semiconductor device may be electrically coupled to outside with one redistribution layer. Therefore, the semiconductor device needs fewer components, compared to a semiconductor device that needs two redistribution layers in accordance with Document 2. It is therefore possible to reduce a manufacturing cost of the semiconductor device. Further it is possible to reduce a height of the semiconductor device compared to a semiconductor device having two redistribution layers, because the semiconductor device needs only one redistribution layer.

It is preferable that the upper face of the bump electrode and the upper face of the molding portion are flat. With the structure, it is easy to form the redistribution layer on the upper face of the molding portion with a sputtering method, a plating method or the like. It is therefore possible to reduce the manufacturing cost of the semiconductor device.

It is preferable that an interval between each of the outer connection electrodes is larger than that between each of the bump electrodes. With the structure, it is easy to determine a position of the semiconductor device when the semiconductor device is connected to outside with the outer connection electrode, even if the semiconductor chip is very small. An electrical short between each of the outer connection electrodes is restrained when the interval between each of the outer connection electrodes is long. It is therefore possible to use a large outer connection electrode. It is therefore possible to improve connection strength between the semiconductor device and an external component.

The semiconductor device may further include a substrate that is fixed to a lower face of the semiconductor chip.

It is preferable that the substrate is a silicon substrate. A warpage amount of a silicon substrate caused by heat is less than that of a glass epoxy substrate. It is therefore possible to manufacture a plenty of the semiconductor devices all together if the silicon substrate is used. It is therefore possible to reduce the manufacturing cost of the semiconductor device.

The semiconductor device may further include an insulating portion. The insulating portion may cover an entire side face and an entire upper face of the redistribution layer. And a part of the outer connection electrode may be exposed. With the structure, it is possible to restrain the electrical short between the outer connection electrodes with the insulating portion. Therefore, the yield ratio of the semiconductor device may be improved. And the manufacturing cost of the semiconductor device may be reduced.

According to an aspect of the present invention, preferably, there is provided a method of manufacturing a semiconductor device including: forming a bump electrode on an upper face of a semiconductor chip; fixing the semiconductor chip to an upper face of a substrate; forming a molding portion that seals an entire of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed; forming a redistribution layer on an upper face of the molding portion so that the redistribution layer is electrically coupled to the bump electrode; and forming an outer connection electrode on an upper face of the redistribution layer so that the redistribution layer is electrically coupled to the bump electrode via the redistribution layer. With the method, it is possible to manufacture a semiconductor device that may be electrically coupled to outside with one redistribution layer. It is therefore possible to reduce a manufacturing cost of the semiconductor device, because the semiconductor device needs fewer components. Further, it is possible to reduce a height of the semiconductor device, because the semiconductor device needs only one redistribution layer.

It is preferable that the substrate is a silicon substrate. A warpage amount of a silicon substrate caused by heat is less than that of a glass epoxy substrate. It is therefore possible to manufacture a plenty of the semiconductor devices all together if the silicon substrate is used. It is therefore possible to reduce the manufacturing cost of the semiconductor device.

It is preferable that the step of forming the molding portion includes arranging the substrate in a mold having a recess and forming the molding portion so as to seal the semiconductor chip. With the method, it is possible to arrange a wafer to be divided into semiconductor devices in the mold having the recess. It is therefore not necessary to provide a mold according to the size of each semiconductor device having different size from each other, when a various kinds of the semiconductor devices are manufactured. And it is therefore possible to reduce the manufacturing cost of the semiconductor device.

It is preferable that the step of forming the molding portion includes fabricating the upper face of the molding portion and an upper face of the bump electrode to be flat. With the method, it is possible to form the redistribution layer accurately on the upper face of the molding portion with a sputtering method, a plating method or the like. It is therefore possible to improve the yield ratio of the semiconductor device. And it is possible to reduce the manufacturing cost of the semiconductor device.

The method may further include removing the substrate after forming the outer connection electrode. With the method, it is possible to reduce the height of the semiconductor device, because the substrate is removed.

It is preferable that the step of removing the substrate includes reducing a thickness of the semiconductor chip and a thickness of the molding portion. With the method, it is possible to reduce the height of the semiconductor device.

It is preferable that the method further includes forming an insulating portion after forming the redistribution layer, and the insulating portion is formed so that the insulating portion covers an entire side face and an entire upper face of the redistribution layer and a region of the redistribution layer where the outer connection electrode is to be connected is exposed. With the method, the electrical short between each of the outer connection electrodes is restrained, because the insulating portion is provided. It is therefore possible to improve the yield ratio of the semiconductor device. And it is possible to reduce the manufacturing cost of the semiconductor device.

The method may further include individuating the semiconductor device after forming the outer connection electrode. With the method, it is possible to manufacture the semiconductor chip having a desirable quantity of the semiconductor chip.

While the above description constitutes the preferred embodiments of the present invention, it will be appreciated that the invention is susceptible of modification, variation and change without departing from the proper scope and fair meaning of the accompanying claims.

The present invention is based on Japanese Patent Application No. 2007-048693 filed on Feb. 28, 2007, the entire disclosure of which is hereby incorporated by reference. 

1-20. (canceled)
 21. A package, comprising: a substrate; a semiconductor chip comprising a first surface adjacent to the substrate and a second surface on the opposite side of the semiconductor chip from the first surface, wherein the semiconductor chip comprises a plurality of contacts disposed on the second surface; an encapsulating layer disposed over the second surface of the semiconductor chip and over the plurality of contacts; an insulating layer disposed over the encapsulating layer; and a plurality of connection terminals disposed in the insulating layer.
 22. The package of claim 21, wherein the contacts comprise bump contacts.
 23. The package of claim 21, wherein the insulating layer has a third surface adjacent to the encapsulating layer and has a fourth surface on the opposite side of the insulating layer from the encapsulating layer, and wherein the connection terminals extend beyond the fourth surface.
 24. The package of claim 21, further comprising a fixing material disposed between the substrate and the first surface of the semiconductor chip.
 25. The package of claim 21, wherein the substrate comprises silicon.
 26. The package of claim 21, wherein the encapsulating layer comprises epoxy resin.
 27. The package of claim 21, wherein the connection terminals comprise gold. 